A phase-locked loop (PLL) is a frequency control system commonly used in a wide range of circuit designs, including, clock generation, clock recovery, spread spectrum, de-skewing, clock distribution, jitter and noise reduction, frequency synthesis, just to name a few. The operation of PLL is based on the phase difference between an input signal and a feedback of a voltage-controlled oscillator (VCO). PLL is widely used as clock generator in devices and hosts supporting high speed transmission protocols, such as, USB2.0, as an important component for synchronization for data transmission. FIG. 1 shows a schematic view of a conventional PLL. As shown in FIG. 1, a conventional PLL includes a phase frequency detector (PFD) 101, a loop filter 102, a VCO 103 and a divider 104. As shown in FIG. 1, PFD 101 receives a reference signal 110 and a feedback signal 104a from divider 104, and outputs a control signal 101a indicating whether the feedback signal is lagging or leading the reference signal. Loop filter 102 converts control signal 101a into a voltage signal 102a to be used by VCO 103 as a bias. VCO 103, based on voltage signal 102a, oscillates faster or slower to generate an output signal 103a. Output signal 103a is also fed to divider 104 to become the feedback signal 104a prior to feeding to PFD 101. In this manner, PLL is able to generate a stable output signal, which is also the reason why PLL is widely used as a clock generator in addition to other applications. In the scenario of clock generator, output signal 103a is the clock provided to the remaining circuits in the device for further controlling and synchronization of the operations of the device.
However, in a conventional PLL, reference signal 110 is usually from a fixed external source, such as, a crystal able to generate clock, as shown in FIG. 1. Final output signal 103a is usually a signal having a frequency that is a harmonic of the external crystal. For example, for PLL used in a USB2.0 application, a 480-MHz clock rate may be generated by using a 12 MHz crystal as the source of reference signal 110.
Generally, the phase frequency detector often used in a conventional PLL design relies on the relative timing of the edge, i.e., phase, of the feedback signal and the reference signal. In this situation, a constant output proportional to the phase difference is produced when both signals are at the same frequency. In other words, the phase detection relies on the comparison of the rising or falling edge. On the other hand, a logic gate-based phase detector used in PLL provides the advantage of quickly forcing the VCO to synchronize with the reference signal even when the frequency of the reference signal is substantially different from the initial output frequency of the VCO. FIG. 2 shows a conventional phase detection mechanism based on the edge alignment. This edge alignment requirement imposes restriction on certain application, such as, in high speed applications.
Another restriction of the conventional phase frequency detector is that a fixed external source is required. This not only adds the cost of the device, but also prohibits the flexibility of the design. It is thus advantageous to devise a novel phase detection mechanism for flexible PLL designs and lowering manufacturing cost.